(1) Field of the Invention
The invention relates to an integrated circuit memory device and, more particularly, to a nonvolatile memory device based on a MONOS cell.
(2) Description of the Prior Art
Memory circuits are a vitally important part of the art of electronic devices. Memory circuits are used to store operating programs and data and are used a wide variety of control and information systems. Memory circuits are typically divided into two main types: volatile and nonvolatile. In a volatile memory, the contents of the memory storage devices are sustained only as long as the power supply to the memory is maintained. In a nonvolatile memory, the data is stored in such a way that the data contents are not lost, even if power is lost.
A typical example of a nonvolatile memory cell is the electrically erasable, programmable read-only memory or EEPROM. An EEPROM device is essentially a modified MOS transistor wherein a charge may be stored on a floating gate structure. The floating gate is constructed in such a way that the presence or absence of charge will cause a large shift in the threshold voltage of the transistor. Further, the floating gate is surrounded by dielectric material such that the charged state of the floating gate is maintained indefinitely regardless of the power supply. The floating gate is typically constructed using a polysilicon layer overlying the circuit substrate with a thin gate oxide therebetween.
Referring now to FIG. 1, another example of a nonvolatile memory device is shown. This device 47 is called a metal oxide-nitride-oxide silicon, or MONOS cell 47. The exemplary MONOS structure is shown as a simplified cross section and is similar to that disclosed in U.S. Pat. No. 6,248,633 to Ogura et al commonly assigned with the present invention. The MONOS structure 47 comprises a complex MOS gate overlying a substrate 10. The MOS gate comprises a wordline gate 20 and two control gates 26 and 28. The wordline gate 20 comprises a conductive layer 20 overlying the substrate 10 with a gate oxide layer 18 therebetween. The wordline gate 20 controls the wordline channel region 42. The first control gate 26 comprises a conductive layer 26 overlying the substrate 10 with a complex dielectric layer 30, 32, and 34 therebetween. The second control gate 28 comprises a conductive layer 28 overlying the substrate 10 with a complex dielectric layer 36, 38, and 40 therebetween. Each control gate 26 and 28 controls a control gate channel region 44 and 46. In addition, first and second doped regions 14 and 16 form source/drain regions for the MONOS cell 47. The overall cell is arranged such that, if all of the channel regions are ON and a drain-to-source bias is established, then current will flow from the drain 14 to the source 16 (or visa versa depending on the bias) through the first control gate channel region 46, the wordline gate channel region 42, and the second control gate channel region 44.
The threshold voltage of the wordline gate 20 is constant and depends on the doping of the substrate 10 in the wordline gate channel region 42 and on the thickness of the gate oxide layer 18. The threshold voltages of the first control gate 26 and of the second control gate 28 are not constant, however, because of the complex dielectric layers 30, 32, and 34 and 36, 38, and 40, respectively. The first complex dielectric layer 30, 32, and 34 comprises a stack of oxide 30, nitride 32, and oxide 34, or ONO. The second complex dielectric layer 36, 38, and 40 comprises a stack of oxide 36, nitride 38, and oxide 40, or ONO. The ONO stacks act as a dielectric layer during low voltage operation, such as when the cell is in standby mode or is being read. However, during a programming or erasing event, it is possible to cause electrons or holes to move across the oxide layers of the ONO stack such that the nitride layer is charged to a negative or a positive potential. It is possible, for example, to bias the first control gate 26, the source/drain region 16, and the substrate 10 such that charges (electron or hole) will move across either the lower oxide layer 30 or across the upper oxide layer 34 to charge or to discharge the nitride layer 32. Likewise, the second control gate 28, source/drain region 14, and the substrate 10 may be biased such that charges (electron or hole) will move across either the lower oxide layer 36 or across the upper oxide layer 40 to charge or to discharge the nitride layer 38.
If the MONOS cell 47 is formed on a p-type substrate, with n-type source and drain regions 14 and 16, then the threshold voltages for the wordline gate 20 and for the control gates 26 and 28 are typically positive. That is, a large enough positive voltage on any of the gates will invert the underlying channel regions to allow for current flow from drain to source. The threshold voltages of the first and second control gates 26 and 28 will vary with the charged state of the nitride layers 32 and 38 of each of the control gates. These nitride layers 32 and 38 may be thought of as storage sites. If, for example, a negative charge (electron) is stored on the first control gate storage site 32, then the value of the threshold voltage of the first control gate 26 will be larger than if the first control gate storage site 32 is neutrally or positively charged.
The process of storing negative charge on a storage site 32 or 38 of the MONOS cell 47 is called programming. The process of removing this negative charge from the storage site 32 or 38 is called erasing. By this convention, a programmed cell has a larger threshold voltage and an erased cell has a lower threshold voltage. This convention may be reversed such that a cell is programmed by removing negative charge and is erased by storing negative charge.
The MONOS cell 47 is also shown in schematic form. Three transistors, C1, W, and C2 are formed in series between the drain D and the source S. The wordline gate transistor W acts like a normal MOS transistor. The control gate transistors C1 and C2 act like nonvolatile MOS transistors where the charged state of the nitride layer determines the threshold voltage of the device. Each transistor has a gate that is described by its transistor. The wordline gate is designated WG, the first control gate is designated CG1, and the second control gate is designated CG2. It is clear from the schematic that all three transistors CG1, W, and CG2 must be turned ON in order to conduct current from drain D to source S. In addition, the MONOS cell 47 provides two storage sites per cell.
The method of formation of the MONOS cell 47 is described in U.S. Pat. No. 6,248,633 to Ogura et al as referenced above. Of special consideration to the present invention is the formation of the control gates 26 and 28. The control gate layer 26 and 28 is typically a single, conformal layer of polysilicon that is deposited overlying a previously formed wordline gate layer 20. Note that a dielectric layer 22 separates the wordline gate layer 20 from the control gate layer 26 and 28. The control gate layer 26 and 28 is then anisotropically etched down to form spacers on the sidewalls of the wordline gate layer 20 with the dielectric layer 22 therebetween. By forming the control gates 26 and 28 in this fashion, a very compact MONOS cell 47 is fabricated wherein the control gates 26 and 28 are self-aligned to the wordline gate 20 without a photo mask step.
Several prior art inventions relate to nonvolatile memory and, in particular, to MONOS-based memory devices. U.S. Pat. No. 6,248,633 to Ogura et al describes methods to form and to operate a MONOS Memory. A multiple level programming method using ballistic injection is disclosed. U.S. Pat. No. 6,469,935 to Hayashi shows an array architecture for a MONOS-based nonvolatile memory. The bit line array is connected by metal lines such that four memory sites share a single bit line contact. Wordlines and control lines run in first direction while bit lines run in the orthogonal direction. U.S. Pat. No. 6,477,088 to Ogura et al describes methods to program and to erase cells on a twin MONOS array. U.S. Application 2003/0032243 to Ogura et al describes a nonvolatile memory array comprising twin MONOS cells and arranged in a NAND stack. However, the cells do not comprise separate control gates. U.S. Pat. No. 6,650,567 to Cho et al describes a nonvolatile memory comprising floating gate devices in a NAND array.
The above-described prior art MONOS-based memories have several disadvantages. Where a diffusion bit array is used, such as in U.S. Pat. No. 6,248,633 to Ogura et al, the manufacturing process is complex and is not compatible with a standard MOS logic process. Where a metal bit array method is used, such as in U.S. Pat. No. 6,469,935 to Hayashi, the process is simpler because the wordline gates do not need to be cut between cells. However, there is an area penalty associated with the metal bit process because one bit line contact is required for every two memory cells, or every four memory sites. An important purpose of the present invention is to improve the layout density of the MONOS-based memory device.